1. Introduction

The 800ZR generation is still filling out router faceplates, and the next rate class is already being argued over inside the Optical Internetworking Forum (OIF). 1600ZR and 1600ZR+ are not a simple doubling of 800ZR the way 800ZR doubled 400ZR. Doubling line rate this time forces the symbol rate toward the 240 gigabaud (GBd) range, and every component bandwidth in the analog chain has to widen with it, while the power budget that pluggable form factors allow is not growing at the same pace. This short article covers three specific engineering shifts the 1.6T generation forces — symbol-rate scaling, the digital signal processor (DSP) power ceiling, and host thermal design — and closes with where the OIF 1600ZR, 1600ZR+, and 1600CL projects and the IEEE 802.3dj task force actually stand as this is being written.

The context matters because these are not laboratory demonstrations. The 400ZR and 800ZR generations moved coherent optics out of dedicated transponder shelves and into router line cards, a shift covered in the MapYourTech primer on IP over DWDM architecture. 1600ZR-class modules extend that same faceplate-pluggable model to 1.6 Tb/s per wavelength, and the constraints that made 800ZR difficult — power, thermal density, and analog bandwidth — do not relax at the next rate class. They tighten.

2. Why Baud Rate Became the Bottleneck

A coherent line rate is set by three levers: symbol rate, modulation order, and the code rate left over after forward error correction (FEC) overhead. The 400ZR and 800ZR generations held modulation order fixed at DP-16QAM and let symbol rate carry almost all of the rate increase. 400ZR runs at 59.8–60.1 GBd depending on the FEC variant in use, a standard-specified value from the OIF 400ZR Implementation Agreement. 800ZR runs at 118.2 GBd with no probabilistic constellation shaping (PCS), and 800ZR+ runs up to 131.35 GBd once PCS is layered on, because shaping the constellation lowers the average information per symbol and the baud rate has to rise to compensate.

Follow that same doubling and 1600ZR lands close to 236–240 GBd, and 1600ZR+ close to 252–262 GBd — figures that OIF contributors and DSP vendors have discussed publicly, though the final Implementation Agreement values are not yet locked. Acacia's public commentary on the project describes this as pushing toward what it calls a "Class 4" baud rate tier near 240 GBd, a vendor-side characterization rather than a published standard number. Reaching it means every analog block in the coherent front end — the digital-to-analog converter (DAC), the analog-to-digital converter (ADC), the driver, and the modulator — needs roughly double the sampling rate and double the analog bandwidth of the 800G generation, since the 800ZR/800ZR+ front end already operates near 120 GHz of analog bandwidth.

Capacity = 2 × Rs × log2(M) × r

where
  Rs  = symbol rate (baud)
  M   = modulation order (16 for DP-16QAM)
  r   = FEC code rate (net bits carried per coded bit)
  2   = the two orthogonal polarizations of dual-polarization transmission

Where 1600ZR+ diverges from a simple baud-rate doubling is its adoption of a dual-subcarrier architecture: instead of one 252 GBd carrier, the signal is split digitally into two subcarriers running near 126 GBd each. Splitting the carrier reduces the equalization-enhanced phase noise and chromatic-dispersion penalty that a single very-high-baud carrier accumulates over distance, at the cost of added DSP complexity. This mirrors a technique already discussed in the MapYourTech piece on probabilistic constellation shaping, where shaping and reach trade against each other; here, subcarrier count and reach trade against each other in a similar way.

Takeaway: The 1.6T generation is not a new modulation format. It is DP-16QAM pushed to roughly 240 GBd for 1600ZR, or split into two ~126 GBd subcarriers with probabilistic constellation shaping for 1600ZR+ — and the honest bottleneck is analog component bandwidth, not DSP cleverness.

3. The DSP Power Ceiling That Will Not Move

Cisco's own 800G coherent pluggable data, presented publicly in 2026, specifies less than 28 W for 800ZR and less than 30 W for 800ZR+ on a 4-nanometer (nm) CMOS DSP with silicon-photonics integration — a vendor-published product specification, not a theoretical figure. That number matters because industry commentary on the 1600ZR project, including remarks attributed to Ciena's optical strategy team in trade coverage of the OIF's work, has been consistent on one point: the roughly 28 W target for 800ZR-class modules is expected to carry forward largely unchanged into 1600ZR, and Nokia's OFC 2026 briefing put the 1600ZR+ target in the 38–40 W range once the dual-subcarrier, PCS-enabled mode is included. That is a vendor claim, not yet a ratified OIF number, but it is the figure multiple vendors have converged on publicly.

Framed as power per bit, an 800ZR module near 28 W over 800 Gb/s works out to roughly 35 milliwatts per gigabit (mW/Gb/s). A 1600ZR+ module at 38–40 W over 1600 Gb/s works out to roughly 24–25 mW/Gb/s — a real efficiency gain per bit, even though the absolute wattage the host has to dissipate goes up. Both figures are calculated from the vendor power targets above, not independently measured, and should be read as approximate rather than fixed.

Getting there depends on the CMOS node. The 800ZR generation already runs 4 nm coherent DSPs; Marvell's publicly announced Electra DSP, built for its COLORZ 1600 module family, moves to a 2 nm node, with sampling to customers expected in the second half of 2026 according to the company's own OFC 2026 announcement. A smaller node lowers energy per computed bit, which is the only lever available once symbol rate — and therefore the raw sample-processing workload of the DSP — has already doubled. The trade-off, discussed at length in the MapYourTech comparison of in-house versus merchant coherent DSP architectures, is that each new node adds meaningfully to non-recurring engineering cost, which is one reason only a small number of DSP vendors are pursuing 1.6T coherent silicon at all.

4. Host Thermal Design for 1.6T Modules

Power that does not leave through the fiber leaves through the module case, and a fixed power ceiling packed into a smaller, denser 1.6T form factor raises power density even when total wattage stays flat. Two pluggable form factors are in play for 1.6T coherent: QSFP-DD1600 and OSFP1600. QSFP-DD relies on a riding heatsink and host airflow, which keeps port density high but caps the power a module can dissipate reliably. OSFP integrates its own heatsink into the module body, which spreads heat more effectively and is the form factor vendors are pairing with the higher-power 1600ZR+ mode; QSFP-DD1600 remains the likely home for lower-power 1600ZR-only modules where backward-compatible port density matters more than headroom.

The router side of the interface is changing at the same time. IEEE's 802.3dj task force, covering 200 Gb/s, 400 Gb/s, 800 Gb/s, and 1.6 Tb/s Ethernet, defines the 200 Gb/s-per-lane PAM4 electrical interface that feeds a 1.6T port over eight parallel lanes — the same lane-doubling pattern used to move from 400G's eight 50G lanes to 800G's eight 100G lanes. The 802.3dj project moved to Working Group Ballot in 2025 and is targeted for completion in the second half of 2026, per IEEE's own project tracking; as with any standard still in ballot, the exact ratification date can still move. Denser electrical lanes on the host side mean host card layouts also have to manage signal integrity and power delivery for eight 200G PAM4 lanes feeding a single coherent module, a system-level constraint on top of the module's own thermal budget.

None of this happens in isolation from the rest of the shelf. A line card carrying multiple 1.6T coherent ports multiplies whatever the per-module thermal number turns out to be, which is the same scaling problem already covered in the MapYourTech analysis of the power-per-bit trade-off in router optics and in the broader trends analysis of the pluggable optics market. Chassis airflow and per-slot power budgets, not the module datasheet in isolation, end up setting how many 1.6T coherent ports a given router platform can actually populate.

5. Where the Standards Work Stands Today

The OIF is running three related projects rather than one. 1600ZR, launched in late 2023, targets an interoperable, cost-optimized 1600 Gb/s interface using single-lambda, single-carrier DP-16QAM for point-to-point data center interconnect (DCI) links up to 120 km amplified — the OIF's own project description, and the closest analog to what 400ZR and 800ZR did at their respective rates. 1600ZR+, launched in early 2024, targets higher performance using fixed hierarchical-tree PCS, oFEC, DP-16QAM, and two digital subcarriers in a low-power DSP, per the OIF's current work page. According to Nokia's OFC 2026 recap, the 1600ZR+ digital baseline was approved in the fourth quarter of 2025, with the Implementation Agreement itself targeted for the third quarter of 2026 — a standards-status figure, not a shipping date. A third project, 1600CL ("coherent lite"), started in the fourth quarter of 2024 and remains behind the other two, still balancing power, performance, and latency trade-offs rather than converging on a baseline.

On the host side, the IEEE 802.3dj task force covers the 200 Gb/s, 400 Gb/s, 800 Gb/s, and 1.6 Tb/s Ethernet PHYs that give 1600ZR-class modules their electrical interface. The project moved to Working Group Ballot in 2025 and industry tracking has placed final completion around mid-to-second-half 2026, though 802.3 ballot schedules have moved before and this is a standards-status estimate rather than a guarantee. Trade coverage of OFC 2026 also notes emerging alternatives worth watching alongside 1600ZR/ZR+: linear-drive and self-homodyne pluggable approaches that trade coherent DSP complexity for reduced power at shorter reach, plus new MSA form factors such as extra-dense pluggable optics (XPO) aimed at even higher aggregate capacity per port. These sit outside the OIF 1600ZR scope but compete for the same DCI use case.

For a closer look at how the 400ZR-to-800ZR transition already played out in practice, including the router power-budget consequences of moving coherent optics into pluggables, see the MapYourTech deep dive on 800G ZR/ZR+ coherent optics and the companion piece on 0 dBm launch-power transceivers, which already flags 1600ZR development as active and targeting the OSFP form factor.

6. Practical Guidelines

• Plan slot power, not just module power. A per-module target near 28–40 W multiplies across every populated port on a line card; verify chassis-level thermal and power budgets before assuming a platform can run a full complement of 1600ZR+ ports, the same lesson already documented for 800ZR in the MapYourTech piece on pluggable optics market trends.
• Match form factor to mode. OSFP1600's integrated heatsink suits the higher-power 1600ZR+ mode; QSFP-DD1600 favors density for the lower-power 1600ZR mode. Confirm which mode a given platform's cooling was designed around before specifying modules.
• Track IA publication dates, not press-release dates. Vendor "1.6T ready" announcements in 2026 are frequently pre-standard samples validated against draft baselines; the 1600ZR+ IA is not expected before the third quarter of 2026, and 1600ZR itself has no published IA date yet.
• Reach and subcarrier count are linked. A single-carrier 1600ZR mode fits short DCI spans; if 1000 km-class reach is the goal, expect the dual-subcarrier 1600ZR+ mode and its higher power draw, not a single-carrier stretch of the base mode.

The broader architectural pattern — coherent optics moving from dedicated transponder shelves into router-hosted pluggables — is unpacked further in the MapYourTech walkthrough of IP-over-DWDM architecture and the comparison of coherent versus direct-detect transceiver selection, both useful background before specifying a first-generation 1.6T deployment.

Takeaway: 1600ZR-class pluggables push symbol rate to roughly double 800ZR's while holding the DSP power target close to flat — a harder engineering problem than either generation change before it, and one still being finalized inside OIF and IEEE 802.3dj through 2026.